A typical PLL circuit is arranged in such a way that the modulation is carried out against the PLL control loop. Such a PLL circuit typically includes a voltage-controlled oscillator having supplied thereto a composite signal on the input side, said composite signal comprising the modulation signal on the one hand and the output signal or error signal of a phase detector on the other.
The output of the voltage-controlled oscillator is simultaneously the output of the PLL circuit, which is coupled back to a phase comparator via a divider circuit, said phase comparator having supplied thereto a fixed reference signal. The phase difference is supplied to the loop filter. In this simple PLL circuit, the modulation signal acts as a disturbance which cannot be compensated for by the phase control loop. Hence, the lowest modulation frequency must necessarily be greater than the loop bandwidth of the loop filter. This standard PLL circuit is to be regarded as being advantageous insofar as it permits a simple channel adjustment, since the output frequency of the PLL circuit corresponds to the product of the divider ratio of the divider and the reference frequency. The same reference quartz can be used for all output frequencies. The circuit permits a linear frequency modulation shift. Such a circuit permits increments of 10 kHz when a suitable reference suppression is effected. As has already been stated, such a PLL circuit with modulation against the PLL control loop is only suitable for modulation frequencies which are greater than the loop bandwidth. This necessitates the exclusive use of dc-free codes for digital modulation, since otherwise lower frequency components in the modulation signal would be eliminated by the PLL control loop.
It follows that, in the field of transmitter technology, the use of a PLL circuit with modulation against the PLL control loop necessitates the use of dc-free codes. Hence, it is necessary to recode an input-side NRZ data stream into dc-free, so-called line codes. In this connection, the problem arises that the asynchronous digital source has to be synchronized with the clock of the coding employed by the transmitter. Hence, preliminary information on the data format of the source is required, viz. especially on the nature of the idle state (idle periods with high or low level), the nature of the synchronization of the bit stream (start bit, stop bit, etc.), the data rate, the rise time of the signals, the lengths of the telegrams, etc. In view of the fact that transparent transmission is demanded, i.e. a transmission without any previous knowledge of the nature and the format of the signal to be transmitted, such restrictions cannot be accepted.
Additional disadvantages of such a circuit with modulation against the control loop are, due to the necessary low loop bandwidth, its sensitvity with regard to frequency modulation disturbances caused by the microphonic effect and antenna feedback. Furthermore, the phase noise is determined by the input quality of the VCO resonator so that the use of a high-quality resonator is necessary; the sensitivity of said resonator with regard to the microphonic effect must be low, and a high isolation attenuation is required from the oscillator to the output.
DE 3533222 A1 already discloses a PLL circuit according to the generic clause, which is suitable to be modulated by a modulation signal having a direct current component. The known PLL circuit comprises a voltage-controlled oscillator whose input side has supplied thereto, on the one hand, the modulation signal via a decoupling capacitor and, on the other hand, an error signal coming from a loop filter. The output-side signal of the oscillator is simultaneously the output signal of the circuit, which is supplied to a loop divider having a fixed loop-divider factor. The output signal of the loop divider is supplied to a phase comparator whose second input has supplied thereto a reference frequency signal and whose output is connected to the loop filter. The reference frequency signal is obtained from the modulation signal via a synthesizer circuit by supplying said modulation signal, after lowpass filtering, to an analog-digital converter which controls a frequency generator via a control bus. A crystal-stabilized frequency is combined with the frequency coming from the frequency generator via a mixer and subsequent divider so as to obtain the desired reference frequency.
Although this known circuit does not entail the initially explained restrictions of conventional PLL circuits with modulation against the PLL control loop, its field of use is, due to the necessary complex circuit components, such as the analog-digital converter and the frequency synthesizer, limited to cases where costs and realization expenditure do not matter.
Also WO 89/07865 discloses a PLL circuit according to the generic clause, which is suitable to be modulated by a modulation signal. The known PLL circuit comprises a voltage-controlled oscillator whose input side has supplied thereto, on the one hand, the modulation signal and, on the other hand, an error signal coming from a loop filter. The output-side signal of the oscillator is simultaneously the output signal of the circuit, which is supplied to a loop divider having a loop-divider factor. The output signal of the loop divider is supplied to a phase detector whose second input is connected to the output of a reference divider with a divider factor, said reference divider being preceded by an upstream reference oscillator and the modulation signal being supplied to said reference oscillator. The output of the phase detector is connected to the loop filter.